This invention relates generally to semiconductor integrated circuit technology, and more particularly the invention relates to multilayer integrated circuits.
The semiconductor integrated circuit is fabricated by the selective introduction of dopants into a single crystal semiconductor body through the use of photoresist masking and chemical etching of dopant barrier layers, diffusion and ion implantation of dopants through the patterns, and electrical interconnection layers. Circuit density is increased as these manufacturing techniques have improved. Typically, the integrated circuits have been fabricated in and on a single surface of a semiconductor substrate.
Greatly increased circuit density can be realized by providing layers of integrated circuits. U.S. Pat. No. 4,233,671 describes a three dimensional processor system in which a read only memory is fabricated in a polycrystalline silicon layer over a single crystal silicon substrate in which the microprocessor is fabricated. An article entitled, "Simple Wafer Fusion Builds Better Power Chips" in Electronics Magazine, Dec. 23, 1985, page 20, discloses the formation of PN junction device structures in which P and N type silicon wafers are bonded together to make power devices. U.S. Pat. Nos. 3,840,888 and 4,317,686 disclose discrete devices fabricated on a supporting substrate.